1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device, a semiconductor system including the same and a test method thereof.
2. Description of the Related Art
A semiconductor memory device includes a plurality of memory cells, and word lines and bit lines in order to read and write data to and from the memory cells. The word lines are driven in response to an active command and a plurality of row addresses. To this end, semiconductor memory devices may further include a control unit for controlling the word lines.
A bit line level equalization signal for precharging the bit lines is activated after the word line is disabled in response to a word line deactivation signal. Word lines are typically used for about 10 years, but word line response time degrades over time as the word lines wear out. Therefore, although the bit line level equalization signal has been designed to activate after the word line is completely disabled, the timing of when the word line is disabled may overlap when the bit line level equalization signal is activated.
FIG. 1 is a waveform diagram illustrating an operation of a conventional semiconductor memory device.
Referring to FIG. 1, a plurality of sub-word lines SWL0 to SWLn may be activated in response to an active command ACT, and then a write operation may be performed in response to a write command WT. After the write operation ends, a bit line level equalization signal BLEQ for precharging bit lines BL may be activated in response to a precharging command PCG. Among the sub-word lines SWL0 to SWLn, it is assumed that the first sub-word line SWL0 may be a non-degraded word line and the second sub-word line SWLn may be a degraded word line as compared with the first sub-word line SWL0. That is, since the second sub-word line SWLn has deteriorated with usage, the slope (i.e. response time) of the second sub-word line SWLn has been reduced.
After the write operation is performed in response to the write command WT, the first sub-word line SWL0 is deactivated in response to a word line deactivation signal (not illustrated) and the bit line level equalization signal BLEQ is activated, so that a precharge operation may be properly performed. However, the timing of when a degraded second sub-word line SWLn is deactivated may overlap when the bit line level equalization signal BLEQ is activated. Therefore, the precharge operation may not be performed properly.